For example, Patent Literature 1 illustrates a configuration where an insulated gate type bipolar transistor (hereinafter referred to as “IGBT”) and a field-effect type transistor (hereafter referred to as “FET”) are connected in parallel. In the invention of Patent Literature 1, in order to miniaturize the FET or the whole device, it is configured that the entire current flows through the IGBT side at the transient state during switching. In particular, it is configured that the IGBT is initially turned on and subsequently the FET is turned on during the turn on. In addition, it is configured that IGBT is turned off after the FET is turned off during the turn off.
Patent Literature 1 describes several techniques to shift the on-state timing and off-state timing of the IGBT and FET. The first technique is to set the threshold voltage of the IGBT to be lower than the threshold voltage of the FET, It is noted that the setting of the threshold voltage is performed by the channel injection amount of impurity during the manufacturing. The second technique is to set the value of the gate interconnection resistor of the FET to be larger than the value of the gate interconnection resistor of the IGBT; and to connect a diode to the gate interconnection resistor of the FET in an anti-parallel manner. The third technique is to connect each of the IGBT and MOSFET to a gate control circuit; and to produce a time difference between the generation of a gate control signal provided to the IGBT and the generation of a gate control signal provided to the FET.
However, with regard to any of the techniques described in Patent Literature 1, it is difficult to take an adequate longer time for the on-timing of the FET, and therefore, the effect of reducing transmission loss, which is caused by the FET, may not be achieved. For example, in a case of the above second technique, the shift of the on-timing of the IGBT and the on-timing of the FET is caused by the variance between the respective capacitances and the variance between the respective values of the gate interconnection resistors. With these variances, it is required to make a margin so as to turn on the FET after the IGBT is switched into a constant state (a saturation state) even when the on-timing of the IGBT makes its closest approach to the on-timing of the FET. Accordingly, the timing for turning on FET has to be set later by the margin and the on-timing of the FET becomes shorter as a result.